1. Field of the Invention
The invention relates to a processor and an instruction control method for executing instructions by dynamic pipeline scheduling. More particularly, the invention relates to a processor and an instruction control method for storing register update data into a data area in a reservation station upon instruction decoding.
2. Description of the Related Arts
Hitherto, in a processor for executing dynamic pipeline scheduling, processes are executed separately by three units: an instruction issuing unit of in-order depending on program order; an instruction executing unit of out-of-order which does not depend on the program order; and a committing unit of the in-order depending on the program order. That is, the instruction issuing unit fetches instructions by the in-order, decodes them, and allows a reservation station to hold the instruction operation (OP code) and an operand. As soon as all operands are prepared in the reservation station and an arithmetic operating unit is made usable, the instruction executing unit speculatively executes the instruction by the out-of-order and obtains a result. The committing unit discriminates a commitment of the instruction on the basis of a branch prediction result or the like, completes the instruction by the in-order, and stores the execution result into a register file or a memory (only in the case of storage). In the processor using such dynamic pipeline scheduling, when a register update instruction is decoded by the instruction issuing unit, control for storing the register update data into a data area in an allocation entry of the reservation station is made, for example, as shown in FIG. 1.
In FIG. 1, for example, when the register update instruction fetched into an instruction word register 200-1 is decoded, if source data does not exist on a register update buffer 204, is not registered into a renaming map 205, and is not update-pending, a data signal 214 is read out from a corresponding general register 202-3 in a general register file 202 and stored into a data area 232 of a reservation station 206. That is, the data signal 214 is read out from the corresponding general register 202-3 in the general register file 202 by a register address signal 212. The data signal 214 is stored into the data area 232 in an allocation entry 206-1 in the reservation station 206 from a selector 216 which has been switched by an OFF state of a pending bit signal 220. A portion obtained by surrounding the data area 232 by a broken line every entry is generally called a data reservation station 234. When the register update instruction fetched in the instruction word register 200-1 is decoded, if the source data exists on the register update buffer 204 and is registered into the renaming map 205 and is update-pending, the data is read out from an allocation buffer 204-3 in the register update buffer 204 as a renaming register of the source data and stored into the data area 232 of the reservation station 206. That is, an allocation buffer address 210 is obtained with reference to the renaming map 205 by a register address signal 224 in the general register 202-3 in which the source data has been stored. Register update data 228 is read out with reference to the allocation buffer 204-3 in the register update buffer 204 by an allocation buffer address signal 226. The register update data 228 is stored into the data area 232 in the allocation entry 206-1 in the reservation station 206 from the selector 216 switched by the pending bit signal 220 which has been set to ON by a pending bit 208 showing that the data is update-pending at this time. With respect to such storage control of the register update data into the data area of the reservation station, that is, into the data reservation station, besides the data in the general register, in a processor using an SPARC instruction architecture, there is a CC register update instruction for updating a condition code (referred to as “CC” in the case of expressing it as an abbreviation in the following description) as source data. A code indicative of a state of a result of an execution of a numerical value arithmetic operating instruction such as negative, zero, overflow, or carry is used as such a condition code. Therefore, also in the case where the CC register update instruction is decoded, control for storing CC register update data into the data reservation station is made as shown in FIG. 2 in a manner similar to the case of the update instruction of the general register.
In FIG. 2, for example, when the CC register update instruction fetched into an instruction word register 300-1 is decoded, if CC source data does not exist on a CC register update buffer 304, is not registered into a CC renaming map 305, and is not update-pending, a CC data signal 314 is read out from a CC register 302 and stored into a CC data area 332 in a reservation station 306. That is, the CC data signal 314 is read out from the CC register 302 by a CC register address signal 312. The CC data signal 314 is stored into the CC data area 332 in a CC allocation entry 306-1 in the reservation station 306 from a selector 316 which has been switched by an OFF state of a CC pending bit signal 320. A portion obtained by surrounding the CC data area 332 by a broken line every entry is generally called a CC data reservation station 334. When the CC register update instruction fetched in the instruction word register 300-1 is decoded, if the CC source data exists on the CC register update buffer 304, is registered into the CC renaming map 305, and is update-pending, CC register update data 328 is read out from a CC allocation buffer 304-3 in the CC register update buffer 304 as a renaming register of the CC source data and stored into the CC data area 332 of the reservation station 306. That is, a CC allocation buffer address 310 is obtained with reference to the CC renaming map 305 by a CC register address signal 324 in the CC register 302 in which the CC source data has been stored. CC register update data 328 is read out with reference to the CC allocation buffer 304-3 in the CC register update buffer 304 by a CC allocation buffer address signal 326. The CC data 328 is stored into the CC data area 332 in the CC allocation entry 306-1 in the reservation station 306 from the selector 316 which has been switched by the CC pending bit signal 320 which has been set to ON by a CC pending bit 308 showing that the data is update-pending in this instance.
However, in the conventional control for storing the source data into the reservation station upon instruction decoding as shown in FIG. 1, if the source data is not update-pending, the processes of the following two stages are executed.                (1) Read-out from the general register 202-3 by the register address signal 212.        (2) Storage of the read-out data signal 214 into the reservation station 206.        
If the source data is update-pending, the processes of the following three stages are executed.                (1) Reference to the renaming map 205 by the register address signal 224.        (2) Read-out from the allocation register 204-3 by the allocation buffer address signal 226.        (3) Storage of the read-out register update data 228 into the reservation station 206.        
Since a logic of the data storage control into the reservation station becomes deep due to the discrimination result about whether the source data is update-pending or not as mentioned above, it becomes a large obstacle to improvement of an operating frequency of the processor. That is, a decoding cycle is determined by the control of three stages of the deep logic.
Such a problem is also true of respect to the control for storing the CC source data into the reservation station upon decoding of the instruction as shown in FIG. 2. In FIG. 2, if the CC source data is not update-pending, the processes of the following two stages are executed.                (1) Read-out from the CC register 302 by the CC register address signal 312.        (2) Storage of the read-out CC data signal 314 into the reservation station 306.        
If the CC source data is update-pending, the processes of the following three stages are executed.                (1) Reference to the CC renaming map 305 by the CC register address signal 324.        (2) Read-out from the CC allocation buffer 304-3 of the CC register update buffer 304 by the CC allocation buffer address signal 326.        (3) Storage of the read-out CC data 328 into the reservation station 306.        
Since a logic of the data storage control into the reservation station becomes deep due to the discrimination result about whether the CC source data is update-pending or not as mentioned above, it becomes a large obstacle to improvement of an operating frequency of the processor.